This invention is in the field of integrated circuit structures and specifically in the field of dielectrically isolated and surface-passivated integrated circuit structures.
Solid-state devices in general and semiconductor devices in particular must have exacting surface properties for successful operation. These devices therefore often fall by surface failure mechanisms. The surface of a PN, p+n, p−n, PN+, pi, ni, metal-oxide, metal-semiconductor, oxide-semiconductor, interfacial rectifying barrier region, or other optoelectromagnetically active signal-translating region (including several coacting, closely spaced rectifying barriers) is especially sensitive to the ambients or contacting materials, contaminants, impurities, or submicon floating or rubbing dust particles. While not limited thereto, the invention is herein mostly described as examples applied to semiconductor devices each having a PN junction as its optoelectromagnetically active region.
My U.S. Pat. No. 3,585,714 describes new methods for simultaneously achieving device isolation, junction surface passivation, novel differential expansion of the junction region peripheral surface in integrated circuits, exposure of material hidden underneath the junction, high-density integrated circuits with round-bottomed, intersecting and isolating grooves, and/or greatly expanded peripheral surface for optoelectrical communication or for the otherwise difficult or impossible yet large (relative to the junction width) electrical contacts. Many advantages are thus obtained including: increased yield; decreased coast; improved junction region surface passivation; complete device isolation; increased packing density in integrated circuits; increased switching speed; reduced nose, instability, leakage current, and electrical shorts; improved breakdown voltage or other device characteristics; controlled carriers generation, movement, and recombination at or near the junction region peripheral surface, and regulated optoelectromagnetic interaction of the active region with the ambient or contacting material.
The same issued U.S. patent describes fully the techniques of selective material removal by mechanical, chemical, or particles bombarding means to achieve differentially expanded junction region peripheral surface particularly in integrated microcircuits. Such a surface is resistant to mobile ions, floating particles, and even micron-size rubbing contaminants and, hence, greatly reduces surface failures of the device. However, such a surface, being bare, is still not perfectly passivated. Surface layers of inert materials must, therefore, be applied or added onto the differentially expanded peripheral surface for added protection. The same patent also teaches the in-situ formation techniques of the isolating grooves made by thermal oxidation or nitridation and ion-implanted oxygen or nitrogen ions.
Unfortunately, these surface layers are far from being perfect or even inert, but are often full of pinholes, microcracks, and other defects. In addition, as pointed out in the issued patent U.S. Pat. No. 3,585,714, these layers must, at the same time, be both thick (but non-flaking) for good protection and yet thin (but non-cracking) for reduced mismatch stresses. They must also be permanently, chemically, and fairly continuously yet firmly bonded to the underlying solid-state materials and, therefore, cannot always or in all respects, be inert or neutral. These layers may, for example, be chemically active by introducing contaminants, diffusants, unwanted impurities, or chemical reactants. They may also be physically active by creating intolerable mismatch stresses and strains, microcracks, dislocations, or other physical defects in the solid state device materials. These layers may even be electronically active by providing unwanted dopants, carrier traps, barrier regions, shorting paths, or inductively-coupled and capacitively-coupled surface streaks or films.